1. Field of the Invention
The present invention relates to microprocessor architectures and, in particular, to a method and apparatus for locking individual selected entries in integrated cache memory.
2. Discussion of the Prior Art
In a conventional single-chip microprocessor architecture, the central processing unit processes instructions and operands which it retrieves from main memory via an external interface bus. Because the central processing unit can execute its functions at a rate much faster than the rate at which the instructions and operands can be retrieved from external main memory, a small high-speed cache memory is often located on-chip between the central processing unit and main memory to minimize the time spent by the central processing unit waiting for instructions and data.
A cache memory is typically organized as a number of blocks of data or instruction information. Each cache block has an associated address tag that uniquely identifies the corresponding block of main memory of which it is a copy. Each time the central processing unit makes an external memory reference, an address tag comparison is made to determine whether the requested data or referenced instruction is stored in the integrated cache. If it is stored in the cache (a "hit"), then the information is provided to the processor from the cache. If it is not stored in the cache (a "miss"), then the information is retrieved from main memory for use by the processor and to replace a block presently stored in the cache in accordance with a replacement algorithm.
Cache memories may be organized into groups of smaller associative memories called sets, each set containing a number of storage locations, referred to as the set size. Thus, for a cache size m, divided into L sets, there are s=m/L storage locations in each set. When an address in main memory is mapped into the cache, it can appear in any of the L sets. For a cache of a given size, searching of the cache sets in parallel for a "hit" can improve access time by a factor of L.
In earlier microprocessor architectures, the cache, while located in the microprocessor's computing cluster, was not integrated on the same semiconductor "microchip" with the central processing unit. Presently available microprocessors utilize a cache memory which is integrated "on-chip" to provide the advantage of further reducing the time delay inherent in going "off-chip" for information. Integrated cache is essential for achieving top microprocessor performance.
An advanced microprocessor architecture that incorporates "on-chip" cache memory is the National Semiconductor Corporation 32-bit NS32532 microprocessor. The on-chip cache of the NS32532 device includes a 512-byte instruction cache and a separate 1024-byte data cache.
The instruction cache of the NS32532 microprocessor stores 512-bytes in a direct-map organization. That is, five-bits of a reference instruction's virtual address select 1 of 32 instruction cache sets. Each set contains 16-bytes of code and a log that holds address tags comprising the 23 most-significant bits of the physical address for the locations stored in that set.
The instruction cache of the NS32532 device also includes a 16-byte instruction buffer from which it can transfer 32-bits of code per cycle to the loader of the microprocessor's instruction pipeline. If the reference instruction is found in the instruction cache, then the instruction buffer is loaded directly from the selected instruction cache set. If the reference instruction is not found in the instruction cache, then the instruction cache transfers the virtual address of the reference to the memory management unit which translates the virtual address to a corresponding physical address for a bus interface unit. The bus interface unit then initiates a read cycle to load the reference instruction from main memory via the external bus. The pipeline's instruction buffer is then written to one of the sets of the instruction cache in accordance with the replacement algorithm.
The data cache of the NS32532 device stores 1024-bytes of data in a two-way set associative organization. That is, each set of the data cache includes two entries containing 16-bytes and two address tags that hold the 23 most-significant bits of the physical address for locations stored in the two entries. Five-bits of the virtual address of the reference are used to select the appropriate set within the data cache from which to read the two entries. Simultaneously, the integrated memory management unit of the NS32532 device is translating the virtual address and transferring the resultant physical address to the data cache and to the bus interface unit. The data cache compares the two address tags with the physical address while the bus interface unit initiates an external bus cycle to read the data from main memory. If the cache reference is a hit, then the selected data is aligned by the data cache and transferred to the execution unit while the bus interface unit cancels the external bus cycle. If the cache reference is a miss, then the bus interface unit completes the external bus cycle and transfers data from main memory to the execution unit and to the data cache, which updates its cache entry in accordance with its replacement algorithm.
Both the instruction cache and the data cache of the NS32532 microprocessor support an operating mode to lock their contents. This feature can be used in real-time systems to allow faster on-chip access to the most critical subroutines and data.
While providing a highly desirable cache locking feature, the NS32532 microprocessor requires locking of the entire cache contents. In many applications, however, only a portion of the cache is required to store time-critical code and data. Consequently, it is inefficient to require that the entire cache be locked.